Timestamp augmented core instruction trace
Trace-driven profile guided optimization
Learning-based basic-block level performance prediction
A Computing and Sensing I/O Device Model for Pre-Silicon End-to-End SoC Evaluation
End-to-End Hardware-Mechanics Co-Simulation Infrastructure
Scale-Up Datacenter Simulations via Multi-FPGA FireSim
A Chisel implementation of the UCIe chiplet link standard sideband
RV32I 3-stage core with L1 I$ and D$ caches
A Chisel implementation of stereo block matching depth estimation accelerator
Boolean Algebra Circuit and Expression Question Generator
Controlled randomness question variant generation in Priarielearn
CS10: The Beauty and Joy of Computing, Project V Skeleton Code